SDIEN=DISABLED, SSGEN=DISABLED, FORIEN=DISABLED, SCCIEN=DISABLED, SIMCEN=DISABLED, FURIEN=DISABLED, SCANEN=DISABLED, SPSEL=PHASE0, DMAEN=DISABLED, SCANMD=ONCE, PACKMD=UPPER_ONLY, BCLKSEL=LPOSC0, INTLVEN=DISABLED, SPEN=DISABLED
Module Configuration
| SPSEL | Sampling Phase Select. 0 (PHASE0): The ADC samples at SSG phase 0. 1 (PHASE1): The ADC samples at SSG phase 1. 2 (PHASE2): The ADC samples at SSG phase 2. 3 (PHASE3): The ADC samples at SSG phase 3. 4 (PHASE4): The ADC samples at SSG phase 4. 5 (PHASE5): The ADC samples at SSG phase 5. 6 (PHASE6): The ADC samples at SSG phase 6. 7 (PHASE7): The ADC samples at SSG phase 7. 8 (PHASE8): The ADC samples at SSG phase 8. 9 (PHASE9): The ADC samples at SSG phase 9. 10 (PHASE10): The ADC samples at SSG phase 10. 11 (PHASE11): The ADC samples at SSG phase 11. 12 (PHASE12): The ADC samples at SSG phase 12. 13 (PHASE13): The ADC samples at SSG phase 13. 14 (PHASE14): The ADC samples at SSG phase 14. 15 (PHASE15): The ADC samples at SSG phase 15. |
| SPEN | Sampling Phase Enable. 0 (DISABLED): Disable Phase Select. The ADC will always sample on the start-of-conversion trigger selected by the SCSEL field. 1 (ENABLED): Enable Phase Select. The ADC will sample according to the phase selected by the SPSEL field. |
| SSGEN | Synchronous Sample Generator Enable. 0 (DISABLED): Disable the SAR clock output to SSG. 1 (ENABLED): The ADC is the SSG master, and the SAR clock will be output to the SSG block. |
| PACKMD | Output Packing Mode. 0 (UPPER_ONLY): Data is written to the upper half-word and the lower half-word is filled with 0’s. An SCI interrupt is triggered when data is written, if enabled. 1 (LOWER_ONLY): Data is written to the lower half-word, and the upper half-word is filled with 0’s. An SCI interrupt is triggered when data is written, if enabled. 2 (UPPER_FIRST): Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. If SIMCEN is set to 1, the upper half-word represents data from the master ADC (selected by SSGEN) and the lower half-word represents data from the slave ADC. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled. 3 (LOWER_FIRST): Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. If SIMCEN is set to 1, the lower half-word represents data from the master ADC (selected by SSGEN) and the upper half-word represents data from the slave ADC. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled. |
| SIMCEN | Simultaneous Conversion Packing Enable. 0 (DISABLED): Disable simultaneous mode conversion packing. 1 (ENABLED): Enable simultaneous mode conversion packing. |
| INTLVEN | Interleaved Conversion Packing Enable. 0 (DISABLED): Disable interleaved mode conversion packing. 1 (ENABLED): Enable interleaved mode conversion packing. |
| SCANEN | Scan Mode Enable. 0 (DISABLED): Disable ADC scan mode. 1 (ENABLED): Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion. |
| SCANMD | Scan Mode Select. 0 (ONCE): The channel sequencer will cycle through all of the specified time slots once. 1 (LOOP): The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0. |
| DMAEN | DMA Interface Enable . 0 (DISABLED): Disable the ADC module DMA interface. 1 (ENABLED): Enable the ADC module DMA interface. |
| BCLKSEL | Burst Mode Clock Select. 0 (LPOSC0): Burst mode uses the Low Power Oscillator. 1 (APB): Burst mode uses the APB clock. |
| CLKDIV | SAR Clock Divider. |
| SCCIEN | Single Conversion Complete Interrupt Enable. 0 (DISABLED): Disable the ADC single data conversion complete interrupt. 1 (ENABLED): Enable the ADC single data conversion complete interrupt. |
| SDIEN | Scan Done Interrupt Enable. 0 (DISABLED): Disable the ADC scan complete interrupt. 1 (ENABLED): Enable the ADC scan complete interrupt. |
| FORIEN | FIFO Overrun Interrupt Enable. 0 (DISABLED): Disable the data FIFO overrun interrupt. 1 (ENABLED): Enable the data FIFO overrun interrupt. |
| FURIEN | FIFO Underrun Interrupt Enable. 0 (DISABLED): Disable the data FIFO underrun interrupt. 1 (ENABLED): Enable the data FIFO underrun interrupt. |